The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while feature size (such as the smallest component that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs.
One method used by the industry to meet the demands for device density is the adoption of damascene and/or dual-damascene structures for interconnection structures. In a damascene process, an underlying insulating layer is patterned with trenches and/or via holes. Afterwards, a conductor is deposited and polished to target thickness to form a patterned conductor feature. Dual-damascene processes use a similar approach and form and fill two features (such as a trench and a via hole) with a single deposition of conductor.
However, as feature sizes shrink further and density requirements increase, the pitch between features, such as interconnect structures, decreases. As a result, fabrication processes continue to become more difficult to perform. It is a challenge to form interconnection structures with smaller and smaller pitches in a semiconductor device.